1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device, and more particularly relates to a method of manufacturing a stacked semiconductor device having a plurality of semiconductor chips stacked thereon.
2. Description of Related Art
The memory capacity required for semiconductor memory devices such as DRAM (Dynamic Random Access Memory) has been increasing year by year. To satisfy this demand, a memory device called a multi-chip package, which has a plurality of memory chips stacked thereon, has been proposed in recent years. In the multi-chip package, however, a wire that connects each memory chip to a package substrate has to be provided for each chip. Therefore, it is difficult to stack a large number of memory chips.
Meanwhile, another type of semiconductor device having a plurality of memory chips stacked thereon with through silicon vias has been proposed in recent years. In this type of semiconductor device, among through silicon vias provided in the respective memory chips, through silicon vias at the same planar position as viewed from a stacked direction are electrically short-circuited. Accordingly, even when the number of stacked memory chips is increased, the number of electrodes connected to a package substrate is not increased. Therefore, more memory chips can be stacked.
When semiconductor chips with through silicon vias are stacked, a through silicon via on an upper chip has to accurately contact a through silicon via on a lower chip. Therefore, as compared to an operation of stacking chips in the multi-chip package, alignment needs a higher accuracy. As a device having semiconductor chips stacked thereon with through silicon vias, a device described in Japanese Patent Application Laid-open No. 2006-49417 has been known.
However, according to stacked semiconductor devices, there are cases where chips that a planar position of an electrode on a front surface is different from that of an electrode on a back surface are stacked (see Japanese Patent Application Laid-open No. 2009-239256). When these chips are stacked by a bonding tool, the planar position of a chip contacting the bonding tool is different from the planar position of the chip contacting an underlying chip. Consequently, a bending moment is generated on the chips at the time of stacking and these chips may be damaged. Such a problem is particularly conspicuous when the thickness of the chip is made as thin as about 50 μm, for example.